This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern circuitry, current 2-port bitcells used in industry are traditionally 2-CPP (cell poly pitch) that needs to fit both read and write wordlines (WLs) for 2-port bitcell in the 2-CPP pitch. As device geometries are scaled to smaller nodes, the metal resistances typically increase exponentially. The large metal resistance may result in large wordline (WL) resistance-capacitance (RC) and slows down the 2-port memory performance.
In reference to the negative impact on area, the 2-CPP bitcell layout may result in an aspect-ratio that is not favorable at the system-on-chip (SoC) for the memory-macro sizes that are typically used for 2-port memories (less words and more bits). At the SoC level, additional area may be lost around memory that cannot be used in SoC placement or routing.
In reference to the negative impact on performance/timing, the 2-CPP bitcell layout may result in a long wordline that causes a larger resistance and capacitance on the wordline-net, which degrades the performance/access-time of the memory-macro.